package cpu

Import Path
	internal/cpu (on go.dev)

Dependency Relation
	imports one package, and imported by 12 packages

Involved Source Files

	  d cpu.go
		Package cpu implements processor feature detection
		used by the Go standard library.

	    cpu_x86.go
	    cpu.s
	    cpu_x86.s
Package-Level Type Names (only one)

	/* sort by: alphabet | popularity */
	 type CacheLinePad (struct)
		CacheLinePad is used to pad structs to avoid false sharing.


Package-Level Functions (total 2)

	 func Initialize(env string)
		Initialize examines the processor and sets the relevant variables above.
		This is called by the runtime package early in program initialization,
		before normal init functions are run. env is set by runtime if the OS supports
		cpu feature options in GODEBUG.

	 func Name() string
		Name returns the CPU name given by the vendor.
		If the CPU name can not be determined an
		empty string is returned.


Package-Level Variables (total 8)

	  var ARM struct{_ CacheLinePad; HasVFPv4 bool; HasIDIVA bool; HasV7Atomics bool; _ CacheLinePad}
		The booleans in ARM contain the correspondingly named cpu feature bit.
		The struct is padded to avoid false sharing.

	  var ARM64 struct{_ CacheLinePad; HasAES bool; HasPMULL bool; HasSHA1 bool; HasSHA2 bool; HasSHA512 bool; HasCRC32 bool; HasATOMICS bool; HasCPUID bool; IsNeoverse bool; _ CacheLinePad}
		The booleans in ARM64 contain the correspondingly named cpu feature bit.
		The struct is padded to avoid false sharing.

	  var CacheLineSize uintptr
		CacheLineSize is the CPU's assumed cache line size.
		There is currently no runtime detection of the real cache line size
		so we use the constant per GOARCH CacheLinePadSize as an approximation.

	  var DebugOptions bool
		DebugOptions is set to true by the runtime if the OS supports reading
		GODEBUG early in runtime startup.
		This should not be changed after it is initialized.

	  var MIPS64X struct{_ CacheLinePad; HasMSA bool; _ CacheLinePad}
	  var PPC64 struct{_ CacheLinePad; HasDARN bool; HasSCV bool; IsPOWER8 bool; IsPOWER9 bool; IsPOWER10 bool; _ CacheLinePad}
		For ppc64(le), it is safe to check only for ISA level starting on ISA v3.00,
		since there are no optional categories. There are some exceptions that also
		require kernel support to work (darn, scv), so there are feature bits for
		those as well. The minimum processor requirement is POWER8 (ISA 2.07).
		The struct is padded to avoid false sharing.

	  var S390X struct{_ CacheLinePad; HasZARCH bool; HasSTFLE bool; HasLDISP bool; HasEIMM bool; HasDFP bool; HasETF3EH bool; HasMSA bool; HasAES bool; HasAESCBC bool; HasAESCTR bool; HasAESGCM bool; HasGHASH bool; HasSHA1 bool; HasSHA256 bool; HasSHA512 bool; HasSHA3 bool; HasVX bool; HasVXE bool; HasKDSA bool; HasECDSA bool; HasEDDSA bool; _ CacheLinePad}
	  var X86 struct{_ CacheLinePad; HasAES bool; HasADX bool; HasAVX bool; HasAVX2 bool; HasAVX512F bool; HasAVX512BW bool; HasAVX512VL bool; HasBMI1 bool; HasBMI2 bool; HasERMS bool; HasFMA bool; HasOSXSAVE bool; HasPCLMULQDQ bool; HasPOPCNT bool; HasRDTSCP bool; HasSHA bool; HasSSE3 bool; HasSSSE3 bool; HasSSE41 bool; HasSSE42 bool; _ CacheLinePad}
		The booleans in X86 contain the correspondingly named cpuid feature bit.
		HasAVX and HasAVX2 are only set if the OS does support XMM and YMM registers
		in addition to the cpuid feature bit being set.
		The struct is padded to avoid false sharing.


Package-Level Constants (only one)

	const CacheLinePadSize = 64

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